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Low Power CMOS SRAM 128K X 8 Bits
Features:
* Vcc operation voltage : 3.0V~ 3.6V * Low power consumption : 20mA (Max.) operating current 1uA (Typ.) CMOS standby current * High Speed Access time : 25ns (Max.) at Vcc = 3.0V * Automatic power down when chip is deselected * Three state outputs and TTL compatible * Data retention supply voltage as low as 1.2V * Easy expansion with CE\ and OE\ options
UC62LS1008 -20/-25
Description
The UC62LS1008 is a high performance, very low power CMOS Static Random Access Memory organized as 131,072 words by 8 bits and operates from 3.0V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 1uA and maximum access time of 25ns in 3.0V operation. Easy memory expansion is provided enable (CE\), and active LOW output enable (OE\) and three-state output drivers. The UC62LS1008 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The UC62LS1008 is available in the JEDEC standard 32 pin 450mil Plastic SOP, 8mmx20.0mm TSOP (type I), and 8mmx13.4mm STSOP.
PRODUCT FAMILY
Product Family
UC62LS1008HC UC62LS1008FC UC62LS1008GC UC62LS1008AC UC62LS1008HI UC62LS1008FI UC62LS1008GI UC62LS1008AI
Operating Tempature
Vcc Range
Speed (ns)
Vcc=3V(Max.)
Power Consumption STANDBY Operating
Vcc=3.3V(Typ.) 1uA Vcc=3.6V(Max.) 20mA
Package Type
TSOP-32 SOP-32 STSOP-32 DICE TSOP-32 SOP-32 STSOP-32 DICE
0J ~ 70J
3.0V ~ 3.6V
20/25
-40J ~ 85J
3.0V ~ 3.6V
20/25
1uA
20mA
PIN CONFIGURATIONS
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 32 1 31 2 30 3 29 4 28 5 27 6 26 7 25 8 9 UC62LS1008FI 24 10 UC62LS1008FC 23 22 11 21 12 20 13 19 14 15 18 16 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3
BLOCK DIAGRAM
ROW DECODER
ROW Address
ADDRESS INPUT BUFFER
CE2 CE WE OE
A0 - A16
MEMORY ARRAY 128K X 8 Bits
COL Address
COLUMN DECODER SENSE AMPLIFIER & WRITE DRIVER X8 I/O BUFFER
CONTROL INPUT BUFFER
CONTROL BLOCK
CE WE OE
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
UC62LS1008HI UC62LS1008HC UC62LS1008GI UC62LS1008GC
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary
Rev. 1.0 PAGE 1
Low Power CMOS SRAM 128K X 8 Bits
PIN DESCRIPTION
Name A0 - A16 CE\,CE2 Type Input Input Function
Address inputs for selecting one of the 131072 x 8 bit words in the RAM
UC62LS1008 -20/-25
CE\ is active LOW. CE2 is active HIGH. Chip enable must be active when data read from or write to the device. If chip enable is not active, the device is deselected and not in a standby power down mode. The DQ pins will be in high impedance state when the device is deselected.
WE\
Input
The Write enable input is active LOW and controls read and write operations. With the chip selected, when WE\ is HIGH and OE\ is LOW, output data will be present on the DQ pins, when WE\ is LOW, the data present on the DQ pins will be written into the selected memory location.
OE\
Input
The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE\ is inactive.
DQ0 - DQ7 Vcc Gnd
I/O Power Power
These 8 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground
TRUTH TABLE
Mode
Not Selected Not Selected Output Disabled Read Write
WE\
X X H H L
CE\
H X L L L
CE2
X L H H H
OE\
X X H L X
I/O state
High Z High Z High Z DOUT DIN
Vcc Current
ISB,ISB1 ISB,ISB1 ICC ICC ICC
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL VTERM TBIAS TSTG PT IOUT PARAMETER Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current RATING -0.5 to VCC+0.5 -40 to 125 -50 to 150 0.5 10 UNIT V J J W mA
OPERATING RANGE
RANGE
Commercial
AMBIENT TEMPERATURE
0J to 70J
VCC
3.0V ~ 3.6V
CAPACITANCE(1)(TA=25J ,f=1.0MHz)
SYMBOL PARAMETER CONDITIONS MAX. UNIT Input VIN=0V 6 pF CIN Capacitance Input/Output VDQ 8 pF CDQ Capacitance 1. This parameter is guaranteed and not 100% tested.
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary
Rev. 1.0 PAGE 2
Low Power CMOS SRAM 128K X 8 Bits
DC ELECTRICAL CHARACTERISTICS (TA=0J to 70J )
Symbol
VIL VIH IL IOL VOL VOH ICC ISB1 ISB2
UC62LS1008 -20/-25
Comment
Guaranteed Input Low (2) Voltage Guaranteed Input High (2) Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current TTL Standby Current CMOS Standby Current
o
Test Condition
VCC=2.4V VCC=3.6V VCC=3.6V VIN=0V to VCC VCC=3.6V CE\=VIH or OE\=VIH VIO=0V t VCC VCC=3.6V, IOL=2mA VCC=3.0V, IOH=-1mA CE\=VIL,IDQ=0mA, F=Fmax CE\=VIH, VIN=VIH to VIL CE\U VCC-0.2V, VIN=VCC-0.2V to 0.2V
(3)
MIN.
-0.5 2.0 2.4 -
TYP.(1)
1
MAX.
0.8 Vcc-0.2 1 1 0.4 20 1 5
UNITS
V V uA uA V V mA mA uA
1. Typical characteristics are at TA = 25 C. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC .
DATA RETENTION CHARACTERISTICS ( TA=0J to 70J )
Symbol VDR ICCDR tDR tR 1. 2. Comment VCC to Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Test Condition CE\U VCC - 0.2V VINU VCC-0.2V or VINO CE\U VCC - 0.2V VINU VCC-0.2V or VINO 0.2V 0.2V MIN. 1.2 0 See Retention Waveform TRC
(2)
TYP. -
(1)
MAX. 0.5 -
UNITS V uA ns ns
0.05 -
VCC = 1.5V, TA = 25J . tRC = Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM(1) (CE\ Controlled)
Vcc CE
tCDR VIH
Data Retention Mode VDR >= 1.2V CE >= VCC - 0.2V
tR VIH
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary
Rev. 1.0 PAGE 3
Low Power CMOS SRAM 128K X 8 Bits
UC62LS1008 -20/-25
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level VCC/0V 1V/ns 0.5VCC
KEY TO SWITCHING WAVEFORMS
WAVEFORMS INPUTS
MUST BE STEADY
MAY CHANGE FROM H TO L
1269
OUTPUTS
MUST BE STEADY
WILL BE CHANGE FROM H TO L
WILL BE CHANGE FROM L TO H
CHANGE STATE UNKNOWN
AC TEST LOADS AND WAVEFORMS
3.3V
INCLUDING JIG AND SCOPE
3.3V
INCLUDING JIG AND SCOPE
1269
OUTPUT
OUTPUT
MAY CHANGE FROM L TO H
DON'T CARE ANY CHANGE PERMITTED
1404
FIGURE 1A
FIGURE 1B
DOES NOT APPLY
1404
30pF
5pF
TERMINAL EQUIVALENT 667 OUTPUT 1.73V
CENTER LINE IS HIGH IMPEDANCE OFF STATE
ALL INPUT PULSES
VCC
GND
10% 90% 90% 10%
FIGURE 2
1V/ns
1V/ns
AC ELECTRICAL CHARACTERISTICS (TA=0J to 70J , VCC=3.0V~3.6V)
READ CYCLE
JEDEC PARAMETER NAME
tAVAX tAVQV tELQV tGLQV tELQX tGLQX tEHQZ tGHQZ tAXOX
PARAMETER NAME
tRC tAA tCE tOE tCLZ tOLZ tCHZ tOHZ tOH
DESCRIPTION
Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Select to Output Low Z Output Enable to Output Low Z Chip Deselect to Output in High Z Output Disable to Output in High Z Address Chang to Output Change
UC62LS1008-20
Min 20 5 3 5 Typ Max 20 20 10 10 10 -
UC62LS1008-25
Min 25 5 3 5 Typ Max 25 25 10 10 10 -
UNIT
ns ns ns ns ns ns ns ns ns
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary
Rev. 1.0 PAGE 4
Low Power CMOS SRAM 128K X 8 Bits
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
tRC ADDRESS tOH DOUT tAA
UC62LS1008 -20/-25
tOH
READ CYCLE2 (1,3,4)
CE tCLZ (5) DOUT tCE tCHZ (5)
READ CYCLE3 (1,4)
tRC ADDRESS tAA OE tOE CE tOLZ tCLZ(5) DOUT
NOTES: 1. WE\ is high in read cycle. 2. Device is continuously selected when CE\ = VIL 3. Address valid prior to or coincident with CE\ transition low. 4. OE\ = VIL. 5. Transition is measured 500mV from steady state with CL=5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested.
tOH
tOHZ(1,5)
tCE
tCHZ(5)
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary
Rev. 1.0 PAGE 5
Low Power CMOS SRAM 128K X 8 Bits
UC62LS1008 -20/-25
AC ELECTRICAL CHARACTERISTICS (TA=0J to 70J , VCC=3.0V~3.6V)
WRITE CYCLE
JEDEC PARAMETER NAME
tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tWLOZ tDVWH tWHDX tGHOZ tWHQX
PARAMETER NAME
tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOHZ tOW
DESCRIPTION
Write Cycle Time Chip Select to END of Write Address Setup Time Address valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold Time for Write End Output Disable to Output In High Z End of Write to Output Active
UC62LS1008-20
Min 20 15 0 15 15 0 8 0 5 Typ 8 Max 8
UC62LS1008-25
Min 25 15 0 15 15 0 10 0 5 Typ 10 Max 10
UNIT
ns ns ns ns ns ns ns ns ns ns ns
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITECYCLE1(1)
tWC ADDRESS tAW OE tCW(11) CE tAS
(4,10)
tWP(2) tOHZ
WE
DOUT tDW DIN tDH
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary
Rev. 1.0 PAGE 6
Low Power CMOS SRAM 128K X 8 Bits
WRITE CYCLE2(1,6)
tWC ADDRESS tAW CE tAS tWP(2) WE tWHZ DOUT tDW DIN tCW(11)
UC62LS1008 -20/-25
tOH (7) tDH (8)
NOTES: 1. WE\ must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE\ and WE\ low. All signals must be active to initiate a write and any one can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE\ or WE\ going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE\ low transition occurs simultaneously with the WE\ low transitions or after the WE\ transition, output remain in a high impedance state. 6. OE\ is continuously low (OE\ = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE\ is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE\ going low to the end of write.
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary
Rev. 1.0 PAGE 7
Low Power CMOS SRAM 128K X 8 Bits
UC62LS1008 -20/-25
ORDERING INFORMATION
UC62LS1008 AB -- YY
A => GRADE C: COMMERCIAL; 0 ~ 70J I : INDUSTRIAL; -40 ~ 85J B => PACKAGE H : TSOP F : SOP G : STSOP A : DICE YY => SPEED 20: 20ns 25: 25ns
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary
Rev. 1.0 PAGE 8
Low Power CMOS SRAM 128K X 8 Bits
PACKAGE DIMENSIONS
Unit Inch Symbol A A1 A2 b b1 c c1 D E e HD L L1 y c 0.0433O 0.004 0.0040.002 O 0.0390.002 O 0.0090.002 O 0.0080.001 O 0.004~0.008 0.004~0.006 0.4650.004 O 0.3150.004 O 0.0200.004 O 0.5280.008 O 0.0197+0.008 -0.004 0.03150.004 O 0.004 Max 0" ~ 8" 1.100.10 O 0.100.05 O 1.000.05 O 0.220.05 O 0.20.03 O 0.10~0.21 0.10~0.16 11.80.10 O 8.000.10 O 0.500.10 O 13.400.20 O 0.5 +0.2 -0.1 0.800.10 O 0.1 Max 0" ~ 8"
1 2 X(2 X )
UC62LS1008 -20/-25
mm
1 2 X(2 X )
e
1
32
b
HD
S E A T IN G P L A N E "y"
1 2 X(2 X )
16 17
E
G AU G E PLANE
A A2
A
D
"A "
c
A1
0 .2 5 4
A
1 2 X(2 X )
L
L1
S E A T IN G P L A N E
1 32
"A " D E T A IL V IE W
b
W IT H P L A T IN G
c
16 17
c1
BASE M ETAL
b1
S E C T IO N A -A
32 - STSO P
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary
Rev. 1.0 PAGE 9
Low Power CMOS SRAM 128K X 8 Bits
UC62LS1008 -20/-25
Unit Symbol A A1 A2 b b1 c c1 D E e HD L L1 y c
Inch 0.0433O 0.004 0.0040.002 O 0.0390.002 O 0.0090.002 O 0.0080.001 O 0.004~0.008 0.004~0.006 0.7240.004 O 0.3150.004 O 0.0200.004 O 0.7870.008 O 0.0197+0.008 -0.004 0.03150.004 O 0.004 Max 0" ~ 8"
mm 1.100.10 O 0.100.05 O 1.000.05 O 0.220.05 O 0.20.03 O 0.10~0.21 0.10~0.16 18.400 .10 O 8.000.10 O 0.500.10 O 20.000.20 O 0.5 +0.2 -0.1 0.800.10 O 0.1 Max 0" ~ 8"
12X(2X)
12X(2X)
e
HD
1
32
b
SEATING PLANE "y"
12X(2X)
16 17
E
GAUGE PLANE
A A2
A
D
"A"
c
A1
0.254
A
12X(2X)
L
L1
SEATING PLANE
1 32
"A" DETAIL VIEW
b
WITH PLATING
c
16 17
c1
BASE METAL
b1
SECTION A-A
32 - TSOP
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary
Rev. 1.0 PAGE 10
Low Power CMOS SRAM 128K X 8 Bits
Unit Symbol A A1 A2 b b1 c c1 D E E1 e L L1 y c 0.111O 0.007 0.0090.005 O 0.10550.005 5 O 0.014 ~ 0.020 0.014 ~ 0.018 0.006 ~ 0.012 0.006 ~ 0.011 0.8050.005 O 0.4450.005 O 0.5550.012 O 0.0500.006 O 0.0330.010 O 0.0550.008 O 0.004 Max 0" ~ 10" 2.8210 .176 O 0.2290.127 O 2.6800 .140 O 0.35 ~ 0.50 0.35 ~ 0.46 0.15 ~ 0.32 0.15 ~ 0.28 20.4470. 127 O 11.3030. 127 O 14.0970.305 O 1.2700 .152 O 0.8340.25 O 1.3970 .203 O 0.1 Max 0" ~ 10" Inch mm
UC62LS1008 -20/-25
32
17 "A"
1 e D b
16 A
E1
E
c 10X (4X) L1 DETAIL "A" (2:1) A2 b WITH PLATING Seating Plane "y" A1 c c1 b1 SECTION A-A A L
A
BASE METAL
SOP - 32
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary
Rev. 1.0 PAGE 11

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